ADVANCE INFORMATION
VCT 38xxA
The CPU telegram can be stopped after the 2 memory
address bytes. The following I2C telegram subaddress-
ing the data register will continue data transfer to or
from the CPU memory. The data transfer will always
start at the CPU memory address (autoincrement is
not saved).
3.14.1.3. Command Subaddressing
TPU supports a command language, allowing the host
controller to start complex processing inside the TPU
with simple commands (see Section 3.12. on
page 68). Commands have to be sent to the command
subaddress.
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< 22 79 ah al > < 22 7C dd .. >
The command subaddress has to be followed by the
command code. The following data bytes are taken as
command parameters.
Data is directly written into CPU memory without using
the I2C buffer of TPU and without waiting for a stop
condition.
The execution time for commands depends on other
processes running inside the TPU firmware, therefore
the host controller has to read the status register to get
information about the running command before read-
ing command parameter or starting other commands.
3.14.1.2. DRAM Subaddressing
DRAM access is necessary to generate level 2 dis-
plays. The external DRAM can be addressed on byte
level. The maximum DRAM size of 16 Mbit requires a
21-bit memory address pointer. The format of the
DRAM address pointer is shown in Fig. 3–20.
The status register returns information about the com-
mand interface. The ‘command wait’ bit is set during
execution of a command and is reset when a com-
mand is executed completely and read parameters are
available. If a non-existing command is sent to the
TPU, the ‘command invalid’ bit is set. If a command
could not be executed successfully, the ‘command
found no data’ bit is set. In this case the read parame-
ters of this command are not valid.
5-bit Bank
8-bit High
8-bit Low
Fig. 3–20: DRAM address pointer
Reading status from TPU is done by subaddressing
the status register followed by repeated start condition
and slave read address (see Fig. 3–21).
The DRAM subaddress has to be followed by
3 address bytes defining the DRAM address pointer.
The following data byte is written into this address.
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>
DRAM subaddressing always uses autoincrement.
Separate read and write DRAM address pointers are
saved for autoincrement.
Telegrams subaddressing the command interface are
buffered and processed after receiving the stop condi-
tion. Therefore the command code and all necessary
command parameters have to be included in a single
telegram.
The DRAM telegram can be stopped after the 3 ad-
dress pointer bytes. The following I2C telegram subad-
dressing the data register will continue data transfer to
or from the DRAM.
When reading the DRAM, the first data byte the TPU
returns is a dummy byte, which has to be ignored.
3.14.1.4. Data Subaddressing
Writing data to TPU memory is possible by subad-
dressing the data register directly. The data is then
written into memory addressed by the foregoing tele-
gram.
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< 22 7A ab ah al > < 22 7C dd .. >
< 22 7A ab ah al > < 22 7C < 23 dd ..>
Data written to the DRAM subaddress is collected first
in the I2C buffer of TPU and is copied to DRAM when
the buffer is full (48 Bytes) or after stop condition. Dur-
ing the time the buffer is copied to DRAM the TPU will
hold the I2C clock line down.
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Reading data from TPU is done by subaddressing the
data register followed by a repeated start condition and
slave read address (see Fig. 3–21). The returned data
depend on the subaddress selected in the preceding
TPU telegram.
Reading data from the DRAM subaddress is also buff-
ered internally. Reading the first byte will only empty the
I2C buffer. Every time the buffer is empty, the TPU will
copy 48 Bytes from DRAM into the I2C buffer. During
this time the TPU will hold the I2C clock line down.
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Micronas
83
MICRONAS [ MICRONAS ]
