VCT 38xxA
ADVANCE INFORMATION
0270 H
Write
Reset
0
DISPLAY MODE 4
Bit
4
Function
1 = new mosaic mode (single switch to character set 1)
0 = old mosaic mode (static switch to character set 1)
3
2
1
0
0
0
0
0
1 = level 1 display mode (read 40 Byte from display bank)
0 = level 2 display mode (read 86 Byte from display bank)
1 = boxing enable
0 = boxing disable
1 = reveal enable
0 = reveal disable
This bit is taken as flash clock for the WST layer, the frequency should be around 6 Hz.
0273 H
Bit
Write
Reset
0
DISPLAY MODE 5
Function
4
WST layer scan line counter preset (LSB for zoom mode)
WST layer scan line counter preset
3 to 0
0
028E H
Write
Reset
0
DRAM MODE
Bit
4
Function
1 = next CPU write without WEQ but with address increment
0 = normal CPU write mode
3
2
1
0
1
1
1 = reset address pointer and switch off refresh during standbyt
0 = keep address pointer and refresh during standby
1 = display channel enable
0 = display channel disable
1 = slicer channel enable
0 = slicer channel disable
029C H
Bit
Read
Reset
−
ACQ SOFT ERROR COUNTER
Function
5 to 0
6-bit soft error counter
counts number of soft error corrected bytes
counter stops at 63
reset after read
029E H
Read
Reset
−
ACQ SYNC STATUS
Bit
7
Function
1 = field 1
0 = field 2
set at line 624 (PAL) or line 524 (NTSC)
reset at line 313 (PAL) or line 263 (NTSC)
6
−
1 = vertical retrace
0 = vertical window
set at line 628 (PAL) or line 528 (NTSC)
reset at line 624 (PAL) or line 524 (NTSC)
80
Micronas
MICRONAS [ MICRONAS ]
