VCT 38xxA
ADVANCE INFORMATION
10: 1F0A
11: SR2
12: Standby Register 2
22: 1FFC
23: TST4
24: Test Register 4
bit
7
6
5
PWM2
0
4
0
3
2
I2C
0
1
0
MB
0
bit
7
6
0
5
0
4
3
2
1
0
0
r/w
PWM3
w
For testing purposes only
reset
0
0
0
0
reset
0
0
0
0
0
PWM3
r/w1:
r/w0:
Pulse Width Modulator 3
Module active.
Module off.
25: 1FFB
26: TST5
27: Test Register 5
bit
r
7
6
0
5
0
4
3
2
1
0
0
For testing purposes only
PWM2
r/w1:
Pulse Width Modulator 2
Module active.
reset
0
0
0
0
0
r/w0:
Module off.
5.7. Reset Logic
5.7.1. Alarm Function
I2C
r/w1:
r/w0:
I2C-Bus Master Interface
Module active.
Module off.
An alarm comparator on the pin RESQ allows the
detection of a threshold higher than the reset thresh-
old. An alarm interrupt can be triggered with the output
of this comparator.
MB
r/w1:
r/w0:
Memory Banking
Module active.
Module off.
The interrupt source output of this module is routed to
the Interrupt Controller logic. But this does not neces-
sarily select it as input to the Interrupt Controller.
Check section “Interrupt Controller” for the actually
selectable sources and how to select them.
5.6. Test Registers
Test registers are for manufacturing test only. They
must not be written by the user with values other than
their reset values (00h). They are valid independent of
the TEST input state.
The intended use of this function is made, when a sys-
tem uses a 3.3V regulator with an unregulated input. In
this case, the unregulated input, scaled down by a
resistive divider, is fed to the RESQ pin. With falling
regulator input voltage this alarm interrupt is triggered
first. Then the reset threshold is reached and
VCT 38xxA is reset before the regulator drops out.
In all applications where a hardware reset may not
occur over long times, it is good practice to force a
software reset on these registers within appropriate
intervals.
The time interval between the occurrence of the alarm
interrupt and the reset may be used to save process
data to nonvolatile memory. In addition, power saving
steps like turning off other devices may be taken to
increase the time interval until reset. The alarm inter-
rupt is a level triggered interrupt. The interrupt is active
as long as the voltage on pin RESQ remains between
the two thresholds of alarm and reset (see Fig. 5–3 on
page 92).
13: 1FFE
14: TST1
17: TST2
20: TST3
15: Test Register 1
bit
7
6
0
5
0
4
3
2
1
0
0
w
For testing purposes only
reset
0
0
0
0
0
16: 1FFF
18: Test Register 2
bit
w
7
6
0
5
0
4
3
2
1
0
0
For testing purposes only
reset
0
0
0
0
0
5.7.2. Software Reset
The TV controller software can generate a reset via
the Reset Control Register (see page 94). To prevent
the TV controller from carrying out a reset in this case,
the internal CPU reset can be disconnected from the
RESQ pin.
19: 1FFD
21: Test Register 3
bit
w
7
6
0
5
0
4
3
2
1
0
0
For testing purposes only
reset
0
0
0
0
0
90
Micronas
MICRONAS [ MICRONAS ]
