ADVANCE INFORMATION
VCT 38xxA
5.3. RAM and ROM
Table 5–2: Internal Memory Locations
On-chip RAM is composed of static RAM cells. The
RAM will hold all information during reset, as long as
the specified operating voltages are available.
Addresses
Internal Memory
4k Program RAM
I/O Register
000000 − 000FFF
001E00 − 001FFF
002000 − 0023FF
002400 − 019FFF
0A0000 − 0A3FFF
The 64PSDIP Multi Chip Module contains a 128-KByte
Flash EEPROM of the ST M29W010B type. These
devices exhibit electrical Byte program and block erase
functions. Refer to the ST M29W010B data sheet for
details.
1k Bootloader ROM
95k Program ROM
16k Text RAM
5.3.1. Address Map
5.3.2. Bootloader
The following ROM addresses are reserved and can-
not be used to store program code.
A segment of the internal ROM is reserved for boot-
loader code. Via this bootloader code it is possible to
download additional code into the internal RAM and
execute this code. The downloaded code can be used
to program the external Flash EEPROM.
Table 5–1: Reserved (physical) addresses
Addresses
Usage
After reset the bootloader checks the I2C bus pins SDA
and SCL for a special identification sequence. If no
identification sequence is detected, the bootloader
starts the application program code.
Manufacturer ROM ID
reserved for bootloader
Interrupt Vectors
reserved
00FFC6 − 00FFD5
00FFD6 − 00FFD7
00FFD8 − 00FFF7
00FFF8
The bootloader checks the address FFD6/FFD7 of the
external memory if there is a predefined pattern
(A55Ah). If so, it starts the external application soft-
ware else it starts the internal application software.
Control Word (during reset)
00FFF9
NMI Vector (expanded by
Interrupt Controller)
00FFFA − 00FFFB
5.4. Control Register
Reset Vector
00FFFC − 00FFFD
0xFFFE − 0xFFFF
The Control Register CR serves to configure the ways,
by which certain system resources are accessed dur-
ing operation. The main purpose is to obtain a variable
system configuration during IC test.
IRQ/BRK Vector
A 16-Byte address space is reserved as “Manufacturer
ROM ID”. This area contains a unique ROM ID number
which has to be agreed between Micronas and the
customer. Especially the first 6 digits identify customer
and version. As an example a Micronas demo software
is identified like “MI1108 240700 TV”.
Upon each High transition on the RESQ pin internal
hardware reads data from address location 00FFF9h
and stores it to the CR. The state of the TEST pin at
this timepoint specifies which program storage source
is accessed for this read:
– With the TEST pin Low, the control byte is read from
internal program storage (mask ROM). With location
00FFF9h set to FFh, this is the setting for stand-
alone operation.
Table 5–2 shows the internal memory segmentation.
Internal program RAM and ROM can be disabled via
the Control Register (chapter 5.4. on page 87). The
internal text RAM can be disabled via Standby Regis-
ter 0 (see page 89).
– With the TEST pin High, the control byte is read
from external memory via the test bus (for test pur-
poses only).The system will thus start up according
to the configuration defined in address location
00FFF9h and automatically copied to register CR.
All memory locations not available internally will be
addressed as external memory. It is possible to oper-
ate with internal and external memory in parallel, but
overlapping memory segments will always be
addressed internally.
During internal memory access, the pins DB0-DB7,
WExQ and OExQ are tristate. For emulation and test
purposes it is possible to change this behavior via the
Micronas
87
MICRONAS [ MICRONAS ]
