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TPU3035 参数 Datasheet PDF下载

TPU3035图片预览
型号: TPU3035
PDF下载: 下载PDF文件 查看货源
内容描述: 图文电视处理器 [Teletext Processors]
分类和应用: 电视
文件页数/大小: 73 页 / 1175 K
品牌: MICRONAS [ MICRONAS ]
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TPU 3035, TPU 3040  
PRELIMINARY DATA SHEET  
2. Functional Description  
cessing this scratch buffer, the CPU stores reorganized  
teletext lines into the page memory which takes up the  
greatest space in the DRAM capacity. A third part of the  
DRAM holds WST level 2 display data, which are read  
out by the WST layer. The CPU has to generate the dis-  
play data by decoding teletext information from the page  
memory.  
2.1. Conceptional Overview  
The basic idea behind the TPU 3040 concept is the re-  
placement of random logic by software. The still existing  
hardware supports the on-chip CPU in tasks with high  
data rates and ineffective software solutions. Typical  
tasks of a teletext decoder are listed below (realization  
on TPU 3040 in brackets):  
Apart from the WST layer, there is also one additional  
on-chip OSD layer. The OSD layer accesses the on-chip  
memory to read text and character font information. The  
RGB outputs of the OSD layer can have higher priority  
thantheWSTlayeroutputs. Thusitispossibletooverlay  
the teletext display with an additional layer for user guid-  
ance.  
– teletext data acquisition  
– teletext data decoding  
– page generation  
(hardware)  
(software)  
(software)  
(software)  
(hardware)  
(software)  
The CPU memory contains RAM, program ROM and  
character ROM. The character ROM holds the font data  
and is separated from the program ROM to save CPU  
time. The CPU can still access the character ROM via  
a DMA interface including wait cycles. The WST layer  
and the additional OSD layer can also access the CPU  
memory via the same DMA interface.  
– page memory management  
– page display  
– user interface  
Fig. 2–1 shows the functional block diagram of the  
TPU 3040. The software approach is realized using a  
65C02 core with RAM and program ROM on chip. Via  
I/O the CPU is connected to a DRAM interface. The  
DRAM contains an acquisition scratch buffer which is  
filled automatically by the teletext slicer circuit. After pro-  
The CPU is supported by some glue logic such as timer,  
watchdog and interrupt controller and communicates  
2
with the outside world via the I C-Bus.  
6
MICRONAS INTERMETALL  
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