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SDA9410-B13 参数 Datasheet PDF下载

SDA9410-B13图片预览
型号: SDA9410-B13
PDF下载: 下载PDF文件 查看货源
内容描述: 显示处理器,并采用扫描率转换器的嵌入式DRAM技术单位 [Display Processor and Scan Rate Converter using Embedded DRAM Technology Units]
分类和应用: 转换器动态存储器
文件页数/大小: 179 页 / 3137 K
品牌: MICRONAS [ MICRONAS ]
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SDA9410  
5.7  
Preliminary Data Sheet  
Output sync controller (OSCM/S)  
Output sync controller (OSCM/S)  
Signals  
Pin number  
Description  
HOUT  
4
horizontal synchronization signal (polarity programmable, I²C Bus  
parameter 4Ah HOUTPOL, default: high active)  
VOUT  
5
7
vertical synchronization signal (polarity programmable, I²C Bus  
parameter 4Ah VOUTPOL, default: high active)  
BLANK  
free programmable horizontal blanking signal (polarity  
programmable, I²C Bus parameter 49h BLANKPOL, default: high  
active)  
INTERLACED  
6
interlaced signal (can be used for AC coupled deflection circuits)  
Table 67  
Output signals  
The output sync controller generates horizontal and vertical synchronization signals for  
the scan rate converted output signal. The figure below shows the block diagram of the  
OSCM/S and the existing I²C Bus parameters.  
HOUTPOL, HOUTFR, APPLOPD,  
NAPOPD, BLANLEN, PPLOP, RMODE,  
BLANDEL, HORPOSM, HORPOSS,  
HORWIDTHM, HORWIDTHS, HOUTDEL  
HOUT  
HOUT  
HIN  
VIN  
generator  
BLANK  
VOUT  
VOUT  
generator  
INTERLACED  
GMOTION,  
MOVMO,  
MOVPH,  
OPERATION  
mode  
generator  
MOVTYP  
VOUTPOL, VOUTFR,  
NALOPD, ALPFOPD,  
LPFOP, VERPOSM,  
STOPMOM, STOPMOS,  
ADOPMOM  
VERPOSS, VERWIDTHM,  
VERWIDTHS, INTMODE  
Figure 34  
Block diagram of OSCM/S  
Furthermore the output sync controller derives framing signals from the generated  
HOUT and VOUT for the output data processing. The framing signals depend on  
different I²C Bus parameters. The whole output picture is a combination of three  
channels:  
77  
Micronas  
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