SDA 9380 - B21
Preliminary Data Sheet
System description
The Peak drive limit register includes the following bits:
PDLIM3
PDLIM2
PDLIM1
PDLIM0
0
PDLT1
PDLT0
PDLD
- PDLIM3..0: Peak drive limit
1000: minimum level
...
0000: default level
...
0111: maximum level
- PDLT1..0: Peak drive limiter time constant
10: faster
11: fast
00: normal (default)
01: slow
- PDLD:
Peak drive limiter disable
0: peak drive limiter is enabled
1: peak drive limiter is disabled
The RGB control byte 3 register includes the following bits:
SW
0
0
RDCI
SCLEV1 SCLEV0 SCSLP1
SCSLP0
- SW:
Setting of output SWITCH
0: output SWITCH has L-level
1: output SWITCH has H-level
- RDCI:
Input range of DCI
0: 0...2.7V
1: 1.8..2.7V
- SCLEV1..0: Soft clip level relative to peak drive limit
10: 100%
11: 105%
00: 110% (default)
01: infinite
- SCSLP1..0: Soft clipping slope
10: 0.125
11: 0.375
00: 0.625
01: 0.875
Micronas
5-27
2001-01-29
MICRONAS [ MICRONAS ]
