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SDA9380-B21 参数 Datasheet PDF下载

SDA9380-B21图片预览
型号: SDA9380-B21
PDF下载: 下载PDF文件 查看货源
内容描述: EDDC增强偏转器和RGB处理器 [EDDC Enhanced Deflection Controller and RGB Processor]
分类和应用: 商用集成电路
文件页数/大小: 72 页 / 404 K
品牌: MICRONAS [ MICRONAS ]
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SDA 9380 - B21  
Preliminary Data Sheet  
Document Change Note  
DS1  
Date  
Page  
Changes compared to previous issue  
2
31.03.98  
17.07.98  
23.07.98  
23.07.98  
27.07.98  
07.08.98  
Version 02  
3
Document state 03 corresponds to silicon version A11  
block diagram changed  
3
46  
bandwidth of YUV increased (new value 30 MHz)  
Vertical component of SCP changed (not equals internal signal VBL!)  
Pin configuration changed  
27  
4, 5, 6  
09.09.98 14, 17, 20 Description of PMW byte changed  
14.09.98  
16.09.98  
16.09.98  
16.09.98  
16.09.98  
43  
14,15  
24  
SCP output level changed (supply voltage for SCP is V  
DD(MC)  
Sequence of I²C control items changed, new items added  
Bit SLBLKS added to RGB control byte 1  
20  
Detailed description of the I²C item PWM control byte  
25, 26  
Detailed description of the items Average beam current limit character-  
istics, Peak drive limit, Soft clipping  
16.09.98  
18.09.98  
34  
21  
Explanation of the items Peak dark detection top border, bottom border,  
left border, right border  
I²C bit KILLZIP deleted, KILLZIP function remains implemented  
18.09.98 10, 21, 39 I²C bit HSWID deleted  
18.09.98 10, 21, 39 I²C bit HSWMI added  
18.09.98  
10, 39  
Positive and negative polarity of HSYNC allowed (int. normalization)  
20.10.98 1, 3, 10, 39 18.75 kHz line frequency added  
27.10.98 14, 31, 32 End of V-blanking also programmable by VBE if JMP=0  
12.11.98  
19.11.98  
24.11.98  
02.12.98  
04.12.98  
04.12.98  
04.12.98  
18.01.99  
21.01.99  
21.01.99  
22.01.99  
05.02.99  
26.02.99  
31  
21  
4
Specification of end of V-blanking component of SCP changed  
3 MSBs of PLL control byte 1 must be 0 instead of don’t care  
Pin configuration changed  
40  
40  
39  
15  
19  
HSAFE input voltage at 31.25 kHz and 38 kHz specified  
VREFP, VREFH, VREFL are internal reference voltages  
Input BSOIN, delay tD2 changed from 30 lines to 42 lines  
Default value of saturation control changed form 0 to -12  
I²C bus bits NR, NL2...NL0 of Vertical sync byte control deleted  
1, 7, 11 Text changed because the vertical noise reduction has been removed  
11  
5, 6  
7, 8  
37  
Remark for switching to external clock mode added  
Pin description changed  
Description of Black Switch Off (BSO) changed  
VSS, SUBST total voltage differentials added  
15.03.99 2, 14, 46 Higher resolution of D/A output (6 bit -> 8 bit), INL changed (1 -> 2 LSB)  
15.03.99  
15.03.99  
16.03.99  
15, 43  
15, 44  
43  
Contrast setting with resolution of 8 bit instead of 6 bit  
Brightness setting with resolution of 8 bit instead of 6 bit  
NTSC/US matrix changed  
Micronas  
i
2001-01-29  
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