MSP 44x8G
PRELIMINARY DATA SHEET
3.1.2. Description of CONTROL Register
Table 3–3: CONTROL as a Write Register
Name
Subaddress
Bit[15] (MSB)
Bits[14:0]
CONTROL 00hex
1 : RESET
0 : normal
0
Table 3–4: CONTROL as a Read Register
Name Subaddress Bit[15] (MSB)
CONTROL 00hex
Bit[14]
Bits[13:0]
Reset status after last reading of CONTROL: Internal hardware status:
not of interest
0 : no reset occured
1 : reset occured
0 : no error occured
1 : internal error occured
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be reset.
3.1.3. Protocol Description
Write to DSP or Demodulator
S
write
device
address
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK
high low high low
P
Read from DSP or Demodulator
S
write
device
address
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK
high low
S
P
read
device
address
Wait ACK data-byte- ACK data-byte NAK
high low
P
Write to Control or Test Registers
S
write
device
address
Wait ACK sub-addr ACK data-byte ACK data-byte ACK
high
low
Note: S =
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
P =
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from MSP indicating internal error state
Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.
1
0
I2C_DA
S
P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
16
Micronas
MICRONAS [ MICRONAS ]
