MSP 44x8G
PRELIMINARY DATA SHEET
2.8. ADR Bus Interface
2.10. Preemphasis
For the ASTRA Digital Radio System (ADR), the
MSP 4408G, MSP 4418G, and MSP 4458G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 44x8G should be provided on a
feature connector:
When using the Aux output for feeding an external
modulator, a preemphasis can be applied to the right
channel.
The signal is scaled down by −3 dB. An overmodula-
tion protection is included in the algorithm which limits
the output signal to 0 dBFS. Due to the nature of a pre-
emphasis, its gain at high frequencies exceeds 3 dB.
Thus, even with 0 dB input signals and prescaler / vol-
ume set to 0 dB, clipping can occur.
– AUD_CL_OUT
There are three modes present: preemphasis off,
50 µs, and 75 µs. (see Table 3–11on page 29) for the
register settings.
– I2S_DA_IN1, 2, or 3
– I2S_DA_OUT, I2S_WS, I2S_CL
– ADR_CL, ADR_WS, ADR_DA
2.11. Clock PLL Oscillator and Crystal Specifications
For more details, please refer to the DRP 3510A data
sheet.
The MSP 44x8G derives all internal system clocks
from the 18.432 MHz oscillator. In NICAM or in I2S-
Slave mode of the synchronous interface, the clock is
phase-locked to the corresponding source. Therefore,
it is not possible to use NICAM and I2S-Slave mode of
the synchronous interface at the same time.
2.9. Digital Control I/O Pins and
Status Change Indication
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 31). This enables the controlling of external
hardware switches or other devices via I2C-bus.
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note that for the
phase-locked modes (NICAM, I2S-Slave), crystals with
tighter tolerance are required. Please note also, that
the asynchronous I2S3 slave interface uses a different
locking mechanism and does not require tighter crystal
tolerances.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 23).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 25).
Remark on using the crystal:
External capacitors at each crystal pin to ground are
required. They are necessary for tuning the open-loop
frequency of the internal PLL and for stabilizing the fre-
quency in closed-loop operation. The higher the
capacitors, the lower the resulting clock frequency. The
nominal free running frequency should match
18.432 MHz as closely as possible.
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I2C bus interactions are reduced to a
minimum (see “STATUS Register” on page 25 and
“MODUS Register” on page 23).
Clock measurements should be done at pin
AUD_CL_OUT. This pin must be activated for this pur-
pose (see MODUS register on page 23).
14
Micronas
MICRONAS [ MICRONAS ]
