PRELIMINARY DATA SHEET
MSP 34x2G
1
0
I2C_DA
S
P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.5. Proposals for General MSP 34x2G I2C Tele-
grams
3.2. Start-Up Sequence:
Power-Up and I2C Controlling
After POWER ON or RESET (see Fig. 4–20), the IC is
in an inactive state. All registers are in the reset posi-
tion (see Table 3–5 and Table 3–6), the analog outputs
are muted. The controller has to initialize all registers
for which a non-default setting is necessary.
3.1.5.1. Symbols
daw
dar
<
write device address (80hex, 84hex or 88hex)
read device address (81hex, 85hex or 89hex
Start Condition
)
>
Stop Condition
aa
dd
Address Byte
Data Byte
3.3. MSP 34x2G Programming Interface
3.3.1. User Registers Overview
3.1.5.2. Write Telegrams
The MSP 34x2G is controlled by means of user regis-
ters. The complete list of all user registers is given in
the following tables. The registers are partitioned into
the Demodulator section (Subaddress 10hex for writ-
ing, 11hex for reading) and the Baseband Processing
sections (Subaddress 12hex for writing, 13hex for read-
ing).
<daw 00 d0 00>
write to CONTROL register
write data into demodulator
write data into DSP
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
3.1.5.3. Read Telegrams
Write and read registers are 16-bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I2C bus have
to take place in 16-bit words (two byte transfers, with the
most significant byte transferred first). All write registers,
except the demodulator write registers, are readable.
<daw 00 <dar dd dd>
read data from
CONTROL register
<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
3.1.5.4. Examples
<80 00 80 00>
RESET MSP statically
Clear RESET
<80 00 00 00>
For reasons of software compatibility to the
MSP 34x0D, an Manual/Compatibility Mode is avail-
able. More read and write registers together with a
detailed description of this mode can be found in the
“Appendix B: Manual/Compatibility Mode” on page 85.
<80 10 00 20 00 03>
Set demodulator to stand. 03hex
<80 11 02 00 <81 dd dd> Read STATUS
<80 12 00 08 01 20> Set loudspeaker channel
source to NICAM and
Matrix to STEREO
An overview of all MSP 34x2G Write Registers is
shown in Table 3–5; all Read Registers are given in
Table 3–6.
More examples of typical application protocols are
listed in Section 3.4. “Programming Tips” on page 47.
Micronas
23
MICRONAS [ MICRONAS ]
