PRELIMINARY DATA SHEET
MSP 34x2G
2.6.6. Subwoofer in Surround Mode
2.8. I2S Bus Interface
If the channel configuration is set to OFF or
TWO_CHANNEL, the subwoofer signal is created by
combining the left and right channels directly behind
the loudness block using the formula (L+R)/2.
The MSP 34x2G has a synchronous master/slave
input/output interface running on 32 kHz.
The interface accepts two formats:
1. I2S_WS changes at the word boundary
2. I2S_WS changes one I2S-clock period before the
word boundaries.
Note: This is identical to the MSP 34x0G.
If the channel configuration is MULTI_CHANNEL, the
subwoofer signal is created by combining the left and
right channels of the loudspeaker channel and the
center signal (= headphone left) directly behind the
loudness block using the formula (L+R+C)/2. Due to
the fact, that the subwoofer is formed behind all bass/
treble/loudness filters, it is strongly recommended to
have exactly the same setting for these filters in both,
the loudspeaker and center/surround channels when
using the subwoofer output. Any mismatch in these
settings will result in an unbalanced mix of L, C and R
for the subwoofer signal.
All I2S options are set by means of the MODUS and
the I2S_CONFIG registers.
The synchronous I2S bus interface consists of five
pins:
– I 2 S _ D A _ I N 1 , I 2 S _ D A _ I N 2 :
I2S serial data input: 16, 18....32 bits per sample
– I2S_DA_OUT:
I2S serial data output: 16, 18...32 bits per sample
– I2S_CL:
I2S serial clock
2.6.7. Equalizer in Surround Mode
– I2S_WS:
I2S word strobe signal defines the left and right
sample
In the MULTI_CHANNEL mode, the equalizer cannot
be used.
If the MSP 34x2G serves as the master on the I2S
interface, the clock and word strobe lines are driven by
the IC. In this mode, only 16 or 32 bits per sample can
be selected. In slave mode, these lines are input to the
IC and the MSP clock is synchronized to 576 times the
I2S_WS rate (32 kHz). NICAM operation is not possi-
ble in slave mode.
2.7. SCART Signal Routing
2.7.1. SCART DSP In and SCART Out Select
The SCART DSP Input Select and SCART Output
Select blocks include full matrix switching facilities. To
design a TV set with four pairs of SCART-inputs and
two pairs of SCART-outputs, no external switching
hardware is required. The switches are controlled by
the ACB user register (see Table 3–11on page 42).
An I2S timing diagram is shown in Fig. 4–22 on
page 71.
2.7.2. Stand-by Mode
If the MSP 34x2G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off the 5-V, but keeping the 8-V power supply (‘Stand-
by’-mode), the SCART switches maintain their posi-
tion and function. This allows the copying from
selected SCART-inputs to SCART-outputs in the TV
set’s stand-by mode.
In case of power on or starting from stand-by (switch-
ing on the 5-V supply, RESETQ going high 2 ms later),
all internal registers except the ACB register
(page page 42) are reset to the default configuration
(see Table 3–5 on page 24). The reset position of the
ACB register becomes active after the first I2C trans-
mission into the Baseband Processing part (subad-
dress 12hex). By transmitting the ACB register first, the
reset state can be redefined.
Micronas
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MICRONAS [ MICRONAS ]
