MSP 34x2G
PRELIMINARY DATA SHEET
2.9. ADR Bus Interface
2.11.Clock PLL Oscillator and
Crystal Specifications
For the ASTRA Digital Radio System (ADR), the
MSP 3402G, MSP 3412G and MSP 3452G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x2G should be provided on a
feature connector:
The MSP 34x2G derives all internal system clocks
from the 18.432 MHz oscillator. In NICAM or in I2S-
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I2S-Slave mode at the same time.
For proper performance, the on-chip clock oscillator
requires a 18.432 MHz crystal. Note that for the
phase-locked modes (NICAM, I2S-Slave), crystals with
tighter tolerance are required.
– AUD_CL_OUT
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
Remark on using the crystal:
– I2S_WS
External capacitors at each crystal pin to ground are
required. They are necessary for tuning the open-loop
frequency of the internal PLL and for stabilizing the fre-
quency in closed-loop operation. The higher the
capacitors, the lower the resulting clock frequency. The
nominal free running frequency should match
18.432 MHz as closely as possible.
– I2S_CL
– ADR_CL, ADR_WS, ADR_DA
For more details, please refer to the DRP 3510A data
sheet.
Clock measurements should be done at pin
AUD_CL_OUT. This pin must be activated for this pur-
pose (see Table 3–9 on page 30).
2.10.Digital Control I/O Pins and
Status Change Indication
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see Table 3–11on page page 42). This enables the
controlling of external hardware switches or other
devices via I2C-bus.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see Table 3–9
on page 30). In this mode, the pins can be used as
input. The current state can be read out of the STATUS
register (see Table 3–9 on page page 31).
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I2C bus interactions are reduced to a
minimum.
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Micronas
MICRONAS [ MICRONAS ]
