MSP 34x1G
PRELIMINARY DATA SHEET
4.4. Pin Configurations
ADR_WS
NC
ADR_CL
DVSUP
DVSS
I2S_DA_IN2
NC
ADR_DA
I2S_DA_IN1
I2S_DA_OUT
I2S_WS
I2S_CL
I2C_DA
NC
NC
I2C_CL
RESETQ
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
NC 10
STANDBYQ 11
ADR_SEL 12
D_CTR_I/O_0 13
D_CTR_I/O_1 14
NC 15
60 DACA_R
59 DACA_L
58 VREF2
57 DACM_R
56 DACM_L
55 NC
NC 16
54 DACM_SUB
53 NC
NC 17
AUD_CL_OUT 18
TP 19
52 NC
MSP 34x1G
51 SC2_OUT_R
50 SC2_OUT_L
49 VREF1
XTAL_OUT 20
XTAL_IN 21
TESTEN 22
ANA_IN2+ 23
ANA_IN− 24
ANA_IN1+ 25
AVSUP 26
48 SC1_OUT_R
47 SC1_OUT_L
46 CAPL_A
45 AHVSUP
44 CAPL_M
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS
AHVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
ASG
SC2_IN_R
SC2_IN_L
AGNDC
NC
SC4_IN_L
SC4_IN_R
ASG
SC3_IN_L
SC3_IN_R
ASG
Fig. 4–6: 68-pin PLCC package (not intended for new designs)
56
Micronas
MICRONAS [ MICRONAS ]
