PRELIMINARY DATA SHEET
MSP 34x1G
SC2_IN_L
ASG
SC3_IN_R
SC3_IN_L
ASG
SC4_IN_R
SC4_IN_L
AGNDC
SC2_IN_R
ASG
SC1_IN_L
SC1_IN_R
VREFTOP
MONO_IN
AVSS
AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVSUP 49
ANA_IN1+ 50
ANA_IN− 51
ANA_IN2+ 52
TESTEN 53
XTAL_IN 54
XTAL_OUT 55
TP 56
32 CAPL_M
31 AHVSUP
30 CAPL_A
29 SC1_OUT_L
28 SC1_OUT_R
27 VREF1
26 SC2_OUT_L
25 SC2_OUT_R
24 NC
MSP 34x1G
AUD_CL_OUT 57
NC 58
23 DACM_SUB
22 NC
NC 59
D_CTR_I/OUT1 60
D_CTR_I/OUT0 61
ADR_SEL 62
STANDBYQ 63
NC 64
21 DACM_L
20 DACM_R
19 VREF2
18 DACA_L
17 DACA_R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
I2C_CL
RESETQ
I2C_DA
I2S_CL
I2S_WS
I2S_DA_OUT
I2S_DA_IN1
ADR_DA
ADR_WS
NC
NC
NC
I2S_DA_IN2
DVSS
DVSUP
ADR_CL
Fig. 4–10: 64-pin PLQFP package
Micronas
59
MICRONAS [ MICRONAS ]
