MSP 34x0G
DATA SHEET
Contents
Page
Section
Title
6
7
7
8
1.
Introduction
1.1.
1.2.
1.3.
Features of the MSP 34x0G Family
MSP 34x0G Version List
MSP 34x0G Versions and their Application Fields
9
2.
Functional Description
10
10
10
10
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13
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13
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15
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2.1.
Architecture of the MSP 34x0G Family
Sound IF Processing
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.3.
Analog Sound IF Input
Demodulator: Standards and Features
Preprocessing of Demodulator Signals
Automatic Sound Select
Manual Mode
Preprocessing for SCART and I2S Input Signals
Source Selection and Output Channel Matrix
Audio Baseband Processing
SRS WOW
2.4.
2.5.
2.5.1.
2.5.2.
2.5.3.
2.5.4.
2.5.5.
2.5.6.
2.5.7.
2.5.8.
2.5.8.1.
2.5.8.2.
2.5.8.3.
2.6.
BBE High Definition Sound
Micronas VOICE
Automatic Volume Correction (AVC)
Loudspeaker and Headphone Outputs
Subwoofer Output
Quasi-Peak Detector
Micronas BASS (MB)
Dynamic Amplification
Adding Harmonics
Micronas BASS Parameters
SCART Signal Routing
2.6.1.
2.6.2.
2.7.
SCART DSP In and SCART Out Select
Stand-by Mode
I2S Bus Interface
2.8.
ADR Bus Interface
2.9.
Digital Control I/O Pins and Status Change Indication
Clock PLL Oscillator and Crystal Specifications
2.10.
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3.
Control Interface
3.1.
I2C Bus Interface
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.4.1.
3.1.4.2.
3.1.4.3.
3.1.4.4.
3.2.
Internal Hardware Error Handling
Description of CONTROL Register
Protocol Description
Proposals for General MSP 34x0G I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I2C-Controlling
3.3.
MSP 34x0G Programming Interface
2
May 27, 2003; 6251-476-1DS
Micronas
MICRONAS [ MICRONAS ]
