DATA SHEET
MAS 35x9F
Contents, continued
Page
Section
Title
20
21
21
21
2.11.3.
2.11.4.
2.11.5.
2.11.6.
Reset Signal Specification
Control of the Signal Processing
Start-up of the Audio Codec
Power-Down
22
22
22
22
22
22
23
23
27
27
28
28
28
28
29
29
29
29
29
30
30
30
31
31
31
32
32
43
43
44
44
45
45
45
46
52
3.
3.1.
Controlling
I C Interface
2
3.1.1.
3.1.2.
3.1.3.
3.2.
Device Address
2
I C Registers and Subaddresses
Naming Convention
Direct Configuration Registers
Write Direct Configuration Registers
Read Direct Configuration Register
DSP Core
3.2.1.
3.2.2.
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
3.3.2.6.
3.3.2.7.
3.3.2.8.
3.3.2.9.
3.3.2.10.
3.3.2.11.
3.3.2.12.
3.3.3.
3.3.4.
3.3.4.1.
3.3.4.2.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.4.
Access Protocol
Data Formats
Run and Freeze (Codes 0hex to 3hex)
Read Register (Code A
Write Register (Code B
)
hex
)
hex
Read Memory (Codes C
and D
)
hex
hex
Short Read Memory (Codes C4
and D4
)
hex
hex
Write Memory (Codes Ehex and Fhex)
Short Write Memory (Codes E4 and F4
)
hex
hex
Clear SYNC Signal (Code 5hex)
Default Read
Fast Program Download (Code 6
Serial Program Download
)
hex
Read IC Version (Code 7
List of DSP Registers
)
hex
List of DSP Memory Cells
Application Selection and Application Running
Application Specific Control
Ancillary Data
Reading of the Memory Cells “Number of Bits in Ancillary Data” and “Ancillary Data”
DSP Volume Control
Explanation of the G.729A Data Format
Audio Codec Access Protocol
Write Codec Register
3.4.1.
3.4.2.
3.4.3.
3.4.4.
Read Codec Register
Codec Registers
Basic MB Configuration
Micronas
June 30, 2004; 6251-505-1DS
3
MICRONAS [ MICRONAS ]
