MAS 35x9F
DATA SHEET
2. Functional Description
2.1. Overview
2.2. Architecture of the MAS 35x9F
The hardware of the MAS 35x9F consists of a high-
performance RISC Digital Signal Processor (DSP),
and appropriate interfaces. A hardware overview of the
IC is shown in Fig. 2–1.
The MAS 35x9F is intended for use in portable con-
sumer audio applications. It receives parallel or serial
data streams and decodes MPEG Layer 2 and 3
(including the low sampling frequency extensions) and
MPEG 2 AAC. A low bit-rate speech codec, compliant
to the ITU Standard G.729 Annex A, is integrated.
Additional downloadable software modules (SDMI,
other audio/speech encoders/decoders) are available
on request.
2.3. DSP Core
The internal processor is a dedicated DSP for
advanced audio applications.
Mic. Input
(incl. Bias)
Audio Codec
1
2
2
Audio
2
Output
Audio
Proc.
Line Input
A/D
MIX
D/A
DSP Core
Serial
S/PDIF Input 1
S/PDIF Input 2
ALU
MAC
Audio
(I2S, SDO)
Accumulators
ROM
Serial Audio
(I2S, SDI)
S/PDIF
Output
Serial Audio
(stream, SDIB)
Control
V
BAT
Volt.
Mon.
2
I C
DCCF
DCFR
DSP
2
D0
D1
I C
control
Interface
Codec
Registers
V1
V2
Div.
Parallel
I/O Bus
(PIO)
Div.
CLKO
Xtal
18.432 MHz
PLL
Synth.
Osc.
Scaler
÷2
Synthesizer
Clock
Fig. 2–1: The MAS 35x9F architecture
8
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
