MAS 35x9F
DATA SHEET
Contents
Page
Section
Title
5
6
6
7
1.
Introduction
Features
1.1.
1.2.
1.3.
Features of the MAS 35x9F Family
Application Overview
8
8
2.
2.1.
Functional Description
Overview
8
2.2.
Architecture of the MAS 35x9F
DSP Core
8
2.3.
9
2.3.1.
2.3.2.
2.3.2.1.
2.3.2.2.
2.4.
RAM and Registers
9
Firmware and Software
Internal Program ROM and Firmware, MPEG-Decoding
Program Download Feature
Audio Codec
9
9
10
10
10
10
10
10
10
11
11
11
11
11
12
12
12
13
15
15
15
15
15
15
15
15
16
17
17
18
18
18
18
18
18
19
2.4.1.
2.4.2.
2.4.2.1.
2.4.2.2.
2.4.2.3.
2.4.2.4.
2.4.3.
2.4.4.
2.5.
A/D Converter and Microphone Amplifier
Baseband Processing
Bass, Treble, and Loudness
Micronas Bass (MB)
Automatic Volume Control (AVC)
Balance and Volume
D/A Converters
Output Amplifiers
Clock Management
2.5.1.
2.5.2.
2.6.
DSP Clock
Clock Output At CLKO
Power Supply Concept
Power Supply Regions
DC/DC Converters
2.6.1.
2.6.2.
2.6.3.
2.7.
Power Supply Configurations
Battery Voltage Supervision
Interfaces
2.8.
2.8.1.
2.8.2.
2.8.3.
2.8.4.
2.8.5.
2.8.6.
2.9.
I2C Control Interface
S/PDIF Input Interface
S/PDIF Output
Multiline Serial Audio Input (SDI, SDIB)
Multiline Serial Output (SDO)
Parallel Input/Output Interface (PIO)
MPEG Synchronization Output
MP3 Block Input Mode
Functional Description of the MP3 Block Input Mode
Setup
2.10.
2.10.1.
2.10.2.
2.10.2.1.
2.10.2.2.
2.11.
Resync Timeout
Detailed Setup
Default Operation
2.11.1.
2.11.2.
2.11.2.1.
Stand-by Functions
Power-Up of the DC/DC Converters and Reset
Important Advice for Turn-on and Operating Voltage
2
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
