MAS 35x9F
DATA SHEET
Table 3–3: Direct configuration registers
2
I C Sub-
address
(hex)
Function
Name
6A
Control Register (reset value = 3000
)
CONTROL
hex
bit[15:14]
Analog supply voltage range
Code
00
01
AGNDC
1.1 V
1.3 V
recommended for voltage range of AVDD
2.0 ... 2.4 V (reset)
2.4 ... 3.0 V
10
1.6 V
3.0 ... 3.6 V
11
reserved
reserved
Higher voltage ranges permit higher output levels and thus a better signal-to-
noise ratio.
bit[13]
bit[12]
Enable DC/DC 2 (reset=1)
Enable DC/DC 1 (reset=1)
Both DC/DC converters are switched on by default with DCEN = high (1).
2)
bit[11]
bit[10]
Enable and reset audio codec
Enable and reset DSP core
2)
For normal operation (MPEG-decoding and D/A conversion), both, the DSP
core and the audio codec have to be enabled after the power-up procedure.
The DSP can be left off if an audio signal is routed from the analog inputs to
the analog outputs (set bit[15] in codec register 00 0F ). The audio codec
hex
can be left off if the DSP uses digital inputs and outputs only.
bit[9]
bit[8]
Reset codec
Reset DSP core
bit[7]
Enable crystal input clock divider of 1.5
(extended range up to 28 MHz)
1)
bit[6:0]
Reserved, must be set to zero
1)
refer to Section 4.6.3. on page 81
refer to Section 2.11.2.1.
2)
24
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
