DATA SHEET
MAS 35x9F
2
Table 3–2: I C subaddresses
3.2.1. Write Direct Configuration Registers
2
S
DW
W
A
subaddr.
A
d3,d2
A
d1,d0
A
P
Sub-
I C-
Function
address Register
(hex) Name
The write protocol for the direct configuration registers
only consists of device address, subaddress and one
16-bit data word.
Direct Configuration
6A
76
77
CONTROL
DCCF
Controller writes to
MAS 35x9F CONTROL
register
3.2.2. Read Direct Configuration Register
S
DW
W
A
subaddr.
A
S
DR
W
A
Controller writes to first
DC/DC configuration reg-
ister
d3,d2
A
d1,d0
N
P
To check the PUP1 and PUP2 power-up flags, it is
necessary to read back the content of the direct config-
uration registers.
DCFR
Controller writes to
second DC/DC configura-
tion register
DSP Core Access
68
data_write
Controller writes to
MAS 35x9F DSP
69
data_read
Controller reads from
MAS 35x9F DSP
Codec Access
6C
codec_write Controller writes to
MAS 35x9F codec regis-
ter
6D
codec_read Controller reads from
MAS 35x9F codec regis-
ter
Example: I2C write access
DW
S
W
A
A
subaddress
subaddress
A
A
high byte data
A
low byte data
W
N
A
P
P
2
Example: I C read access
S
DW
W
S
DR
W
A
high byte data
A
low byte data
W
W = Wait
A = Acknowledge (Ack)
N = Not Acknowledge (NAK)
S = Start
SDA
SCL
1
0
P
S
P = Stop
2
Fig. 3–1: Example of an I C bus protocol for the MAS 35x9F (MSB first; data must be stable while clock is high)
Micronas
June 30, 2004; 6251-505-1DS
23
MICRONAS [ MICRONAS ]
