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CIP3250A 参数 Datasheet PDF下载

CIP3250A图片预览
型号: CIP3250A
PDF下载: 下载PDF文件 查看货源
内容描述: 组件接口处理器 [Component Interface Processor]
分类和应用:
文件页数/大小: 44 页 / 317 K
品牌: MICRONAS [ MICRONAS ]
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CIP 3250A  
ADVANCE INFORMATION  
the polarity of the Fast Blank signal can be changed via  
Table 2–1: Source selection of soft mixer  
2
2
I C register <12>MIXAMP. The I C register  
<11>FBLOFF influences the phase delay between the  
RGB path and the Fast Blank signal (see Fig. 24).  
<11>  
<06>  
PASSYUV  
Fast Blank  
signal  
Source  
PASSRGB  
0
X
0
1
X
RGB  
Additionally, a delay of 1 to 2 clocks between the Fast  
Blank signal and the RGB-path is programmable via I C  
register <16>FBLDEL. By selecting a positive delay,  
shadowing of characters can be obtained, if the back-  
ground color of the RGB-path is set to black.  
2
1
MIX  
X
YUV/RGB  
YUV  
1
X: dont care  
With the built-in linear mixer, the CIP 3250A is able to  
support simple AB roll techniques between analog input  
(A) and digital YUV input (B):  
2.7.2. Fast Blank Monitor  
2
VideoOut = A * (1 FBLMIX/32) + B * FBLMIX/32,  
controllable via the Fast Blank signal (FBL):  
Bits 0 to 3 of I C register <27> are monitoring the analog  
2
FastBlankinput. ReadingI Cregister<27>Fig. 25dis-  
plays the contents depending on the analog FBL input  
signal.  
FBLMIX = INT[(FBL FBLOFF)* MIXAMP/2] + 16,  
analog fast  
blank input  
with FBL of values from 0 to 63. The mixing coefficient  
FBLMIX resolves 32 steps within the range from 0 to 32  
(dependent on step response chosen via I C register  
2
reading I C  
register <27>  
2
<12>MIXAMP) (see Fig. 24).  
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
0
0
<27>FBLSTAT  
<27>FBLRISE  
<27>FBLFALL  
<27>FBLHIGH  
2
When the I C register bit <16>FBLCLP is enabled, the  
soft mixer operates independently of the analog Fast  
Blank input. FBL is clamped to digital 31 (see Fig. 24).  
Mixing between RGB-path and YUV-path is controllable  
Fig. 2–5: Fast Blank Monitor  
2
via the I C register <11>FBLOFF.  
2.8. FSY Front Sync and AVI Active Video In  
FBL (0...63)  
DIGIT 2000 chroma sync detection  
DIGIT 2000 throughput of 72-bit data and clock  
skew data input for DIGIT 2000  
FBLMIX  
32  
1/2  
0
1
6
6
0
31  
16  
skew data input for DIGIT 3000  
2
fblclp  
fbloff  
mixamp  
I C Registers  
HSYNC as timing reference for clamping pulse gener-  
ator  
Fig. 2–4: Fast Blank Processing  
active video input to indicate valid video data and to  
synchronize chroma multiplex for DIGIT 3000  
2
Selectthe linear mixer or the nonlinear mixer via I C reg-  
ister <12>SELLIN. If the nonlinear mixer is selected, a  
dynamic delay control of the analog RGB/YUV input can  
be chosen, to avoid edge artefacts of the RGB/YUV sig-  
nal (e.g. shading), during transition time of Fast Blank  
The FSY input and the AVI input are used to supply all  
synchronization information necessary. Three basic  
2
modes of operation can be selected via I C registers  
<06>D2KIN, <17>D2KSYNC, <17>SYNCSIM, and  
<17>P72BEN.  
2
signal with the I C register <12>CTRLDLY.  
In some applications, it is desired to disable the control  
by the Fast Blank signal and to pass through the digital  
YUVin path or the analog RGB/YUV path. This is pos-  
sible by adequately programming the I C registers  
<06>PASSYUV and <11>PASSRGB (Table 21).  
In a DIGIT 2000 system environment, the CIP 3250A re-  
ceives the synchronization information at the FSY input  
via the DIGIT 2000 SKEW-protocol. The AVI Input may  
be connected to ground GND or VDD (see section  
2.14.).  
2
Micronas  
9
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