欢迎访问ic37.com |
会员登录 免费注册
发布采购

CIP3250A 参数 Datasheet PDF下载

CIP3250A图片预览
型号: CIP3250A
PDF下载: 下载PDF文件 查看货源
内容描述: 组件接口处理器 [Component Interface Processor]
分类和应用:
文件页数/大小: 44 页 / 317 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号CIP3250A的Datasheet PDF文件第16页浏览型号CIP3250A的Datasheet PDF文件第17页浏览型号CIP3250A的Datasheet PDF文件第18页浏览型号CIP3250A的Datasheet PDF文件第19页浏览型号CIP3250A的Datasheet PDF文件第21页浏览型号CIP3250A的Datasheet PDF文件第22页浏览型号CIP3250A的Datasheet PDF文件第23页浏览型号CIP3250A的Datasheet PDF文件第24页  
CIP 3250A  
ADVANCE INFORMATION  
2
Table 2–10: I C-Bus operation, continued  
Sub-  
Address  
(decimal)  
Label  
Bit No.  
(LSB = 0)  
Typical  
Operation  
Value  
Function  
2
I C registers for OUTPUT FORMATTER  
15  
YUVO  
3
1
1
select video component output format  
0 = output formater off (i.e. RGB or YUV output with format 4:4:4)  
1 = output formater on (i.e. YUV output with format 4:2:2 or 4:1:1)  
16  
ADD16Q  
2
black level of Y (luma) output  
0 = Convert Y black level at output from ITU-R 601 Standard  
to DIGIT 2000 Standard (digital 32)  
1 = Y black level at output unchanged  
15  
15  
MOD411ON  
BINO  
2
4
0
0
UV (chroma) output format  
0 = 4:2:2  
1 = 4:1:1  
UV (chroma) sign of output format  
0 = twos complement  
1 = binary offset  
15  
15  
CDEL  
IND  
10  
0
1
select UV (chroma) output sample from 4:4:4 format  
(0...3)  
5
UV (chroma) output format  
0 = DIGIT 2000  
1 = DIGIT 3000 / orthogonal  
15  
15  
UVSW  
DTI  
7
6
0
0
UV (chroma) multiplex of output format  
0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1  
1 = DIGIT 2000 4:2:2  
UV (chroma) output format  
0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1  
1 = DIGIT 2000 4:2:2  
16  
16  
16  
YDEL  
43  
1
0
0
0
adjust Y (luma) output delay in reference to UV (chroma) output  
(0...3) clocks  
DL422Y  
DL422C  
additional Y (luma) output delay  
(0...1) clocks (DIGIT 3000 4:2:2 / MAC)  
0
additional UV (chroma) output delay  
(0...1) clocks (DIGIT 3000 4:2:2 / MAC)  
2
I C registers for SKEW FILTER  
04  
04  
20  
SKWON  
3
0
1
0
skew correction  
0 = off  
1 = on  
SKWCBS  
SKEWLAT  
2
skew filter active for  
0 = DIGIT 2000 pixel orthogonalization  
1 = DIGIT 3000 pixel orthogonalization  
70  
latch time for sub-pixel skew value (from FSY-/SKEW-protocol) to ad-  
just the processing delays of video data to H-sync (see Fig. 213)  
(0...255)*2 clocks  
2
I C registers for PRIO  
14  
PRIOEN  
7
0
1
1
access to Picture Bus (GL, RC, B output)  
0 = disabled (Picture Bus is tristate)  
1 = enabled (access to Picture Bus possible)  
09  
PRIOSRC  
Source for PRIO request  
0 = PRIO request only if AVO is active  
1 = PRIO request always independent of AVO  
14  
13  
PRIOID  
OVR  
64  
70  
7
0
set PRIO priority  
(0...7)  
override value for PRIO-interface  
20  
Micronas  
 复制成功!