CIP 3250A
ADVANCE INFORMATION
data on YUV bus must be kept dynamically for a half
clock cycle. Thus, capactitvie coupling from other sig-
nals to YUV bus must be avoided or reduced to a toler-
able minimum.
Thisprocedurehasmanyfeatureswhichhaveanimpact
on the appearance of a TV picture:
– real-time bus arbitration (PIP, OSD, ...)
– priorities are software configurable
– different coefficients for different sources
2
2.16. I C Serial Bus Control
Communication between the CIP 3250A and the exter-
2
nal controller is done via I C bus. The CIP 3250A has an
2
2
I C bus slave interface and uses I C clock synchroniza-
2
tion to slow down the interface if required. The I C bus
interface uses one level of subaddressing: one I C bus
2
address is used to address the IC and a subaddress se-
lects one of the internal registers.
The registers of the CIP 3250A have 8 bit data size. All
registers are writeable (except subaddress hex27) and
readable as well. Register bits of parameter addresses,
which are marked with an X in the description field of the
registertable, mustbesettozero. Allregistersareinitial-
ized to zero with reset.
2
Figure 2–12 shows I C bus protocols for read and write
operations of the interface.
S
S
1101110
1101110
W
W
Ack
Ack
0111 1100
0111 1100
Ack
Ack
1 byte Data
1101110
Ack
R
P
2
I C write access
S
Ack
1 byte Data
Nak P
2
I C read access
W
R
Ack
Nak
S
=
=
=
=
=
=
0
1
0
1
Start
Stop
1
0
SDA
SCL
S
P
P
Device Address = 110 1110[R/W]
2
Fig. 2–12: I C Bus Protocol
16
Micronas
MICRONAS [ MICRONAS ]
