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CCU3001 参数 Datasheet PDF下载

CCU3001图片预览
型号: CCU3001
PDF下载: 下载PDF文件 查看货源
内容描述: 中央控制单元 [Central Control Unit]
分类和应用: 外围集成电路
文件页数/大小: 77 页 / 829 K
品牌: MICRONAS [ MICRONAS ]
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CCU 3000-I, CCU 3001-I  
2
Table 2–1: I C and IM bus interface registers  
For example, the software has to work off the following  
sequence (ACK =1) to read a 16-bit word from an I Cde-  
2
vice address 10H (on condition that the bus is not ac-  
tive):  
Address  
Function  
2
2D0H(w)  
generate I C start condition,  
2
transfer Data as I C address,  
and set ACK=1  
–write 21H to  
–write 0FFH to  
–write 0FFH to  
–read dev. address2D6H  
–read 1. databyte 2D6H  
–read 2. databyte 2D6H  
2D0H  
2D2H  
2D4H  
check  
receive  
FIFO empty flag  
(bit 1, 2D7H) be-  
fore read  
2D1H(w)  
2D2H(w)  
same as above, ACK=0  
2
output 8 I C Data bits,  
set ACK=1  
2D3H(w)  
2D4H(w)  
same as above, set ACK=0  
2
output 8 I C Data bits,  
set ACK=1,  
Thevalue21Hinthefirststepresultsfromthedevicead-  
dressinthe7MSBsandtheR/W-bit(read=1)intheLSB.  
If the telegrams are longer, the software has to ensure  
that neither the Control-Data-FIFO nor the Read-FIFO  
can overflow.  
2
generate I C stop condition  
2D5H(w)  
same as above,  
set ACK=0  
2D6H(r)  
2D7H(r)  
receive FIFO  
status flags:  
To write data to this device:  
bit 0  
bit 1  
not used  
–write 20H to  
–write 1. databyte to  
–write 2. databyte to  
2D0H  
2D2H  
2D4H  
1= receive  
FIFO empty  
bit 2  
1= contr-data-  
FIFO half full  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
1= Bus busy  
The bus activity starts immediately after the first write to  
the Control-Data-FIFO. In the I C mode the transmis-  
2
2
I C data ACK  
sion can be synchronized by an artificial extension of the  
Low phase of the clock line. Transmission is not contin-  
ued until the state of the clock line is High once again.  
Thus a slave (software slaves!) can adjust the transmis-  
sion rate to its own abilities.  
2
I C adr ACK  
“OR”ed ACK  
not used  
2D8H(w)  
2D9H(w)  
2DAH(w)  
generate IM-address field  
generate 8 IM-data bits  
2
The I C/IM bus interface is a pure Master system, Multi-  
generate 8 IM-data bits and  
the IM-stop condition  
master busses are not realizable.  
The ident, clock and data terminal pins have open-drain  
outputs with weak pull-up transistors.  
2DBH(w)  
terminal select & speed  
68  
MICRONAS INTERMETALL  
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