CCU 3000-I, CCU3001-I
, CCU 3000-I
CCU 3001, CCU 3001-I
8. Addendum: CCU 3000-I Specification
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20FH
Port 2 Data
Direction Register Port 2
Port 3 Data
Direction Register Port 3
Port 4 Data
Port 5 Mode Register
Port 5 Direction Register
Port 5 Data
8.1. Changes to CCU3000
Instead of the Master/Slave IM bus Interface IM1 of
2
CCU3000, an I C/IM bus Master is used.
Source 3 of the interrupt controller is not connected. Its
priority has to be set to ‘0’.
IR-Input
Port 7 Mode Register
Source 4 of the interrupt controller is connected with
Port81 (Special Input). Falling edges of port 8, bit 1 gen-
erateinterruptsifthepriorityofthisinterruptsourceisnot
21CH
21DH
21EH
21FH
220H
221H
Interrupt controller control byte
Interrupt controller return byte
Interrupt controller priorities source 0 & 1
Interrupt controller priorities source 2 & 3
Interrupt controller priorities source 4 & 5
Interrupt controller priorities source 6 & 7
2
2
setto0. InI CmodeitispossibletoswitchI C_CLKfrom
2
IM1_CLK_Pad to IM1_ID_Pad. Therefore two I C
busses can be driven (see section 8.6. for details).
The CCU 3000-I is available in two different packages,
see pages 71 to 73. All other features are the same as
in CCU3000.
222H
223H
224H
225H
226H
228H
229H
22AH
22BH
Timer 1 control byte 1
Timer 1 control byte 2
Timer 1 control byte 3
Timer 1 prescaler low byte
Timer 1 prescaler high byte
Timer 1 accu low byte
Timer 1 accu high byte
Timer 1 adder low byte
Timer 1 adder high byte
8.2. Definitions
8.3. Interrupt Definitions
Interrupt
Source
Vector (low, high byte)
22CH
22DH
22EH
22FH
230H
232H
233H
234H
235H
Timer 2 control byte 1
Timer 2 control byte 2
Timer 2 control byte 3
Timer 2 prescaler low byte
Timer 2 prescaler high byte
Timer 2 accu low byte
Timer 2 accu high byte
Timer 2 adder low byte
Timer 2 adder high byte
0
1
2
3
4
5
6
7
TIMER1
TIMER2
TIMER3
NC
FFF6, FFF7
FFF4, FFF5
FFF2, FFF3
FFF0, FFF1
FFEE, FFEF
P81
IM-BUS2, Master FFEC, FFED
IM-BUS2, Slave FFEA, FFEB
P87
FFE8, FFE9
FFFC, FFFD
RESET
236H
237H
238H
239H
23AH
23CH
23DH
23EH
23FH
Timer 3 control byte 1
Timer 3 control byte 2
Timer 3 control byte 3
Timer 3 prescaler low byte
Timer 3 prescaler high byte
Timer 3 accu low byte
Timer 3 accu high byte
Timer 3 adder low byte
Timer 3 adder high byte
8.4. Memory Mappings
RAM
ROM
0000H to 01FFH Page 0, 1
0300H to 063FH Page 3, 4, 5, 6
8000H to FFFFH (CCU3001-I only)
Control
byte
FFF9
240H
241H
242H
243H
244H
245H
246H
247H
249H
24AH
24BH
24CH
24EH
Port 6 Data
Direction Register Port 6
Port 7 Data
Direction Register Port 7
Port 8 Data
Direction Register Port 8
IM-Bus 2 control & status
IM-Bus 2 transfer rate
IM-Bus 2 master address
IM-Bus 2 master data low
IM-bus 2 master data high
IM-bus 2 slave 1, IM address 02
IM-bus 2 slave 2, IM address 03
I/O
0200 to 02FF
8.5. I/O Definitions
Address
Function
200H
201H
202H
203H
204H
Clock frequency
Control register
Watchdog
Port 1 Data
Direction Register Port 1
66
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
