CCU 3000C-IC, CUC3U03000-I1,-CI CU 3001-I
CCU 30 , CCU 3000-I
CCU 3001, CCU 3001-I
250H
2D0H
IM-bus 2 slave 3, IM address 04
I C Start Cycle without generation of
where n is the value of bits 0 to 6 and the setting value
(0 = reset state means n = 128). A complete telegram is
assembled by the software out of individual sections.
Each section contains an 8-bit data. This data is written
into one of the nine possible Control-Data registers. De-
pending on the chosen address, a certain part of an I C
or IM bus cycle is generated. By means of correspond-
ing calling sequences it is therefore possible to join even
2
ACK (ACK = ‘1’)
2
2D1H
2D2H
2D3H
2D4H
2D5H
I C Start Cycle with generation of ACK
(ACK = ‘0’)
2
2
I C Resume Cycle without generation
of ACK (ACK = ‘1’)
2
I C Resume Cycle with generation
of ACK (ACK = ‘0’)
very long telegrams (e.g. long data files for auto incre-
2
2
I C Termination Cycle without generation
of ACK (ACK = ‘1’)
ment addressing of I C slaves).
2
I C Termination Cycle with generation of
The software interface contains a 3 byte deep FIFO for
the control-data registers as well as for the received
ACK (ACK = ‘0’)
2
2
2D6H
2D7H
2D8H
2D9H
2DAH
2DBH
I C / IM bus Data from Receive-FIFO
data. Thus all IM and most of the I C telegrams can be
2
I C / IM bus Status
transmitted to the hardware without the software having
to wait for empty space in the FIFO.
IM bus Start Cycle
IM bus Resume Cycle
IM bus Termination Cycle
All address and data fields appearing on the bus are
constantly read and written into the Read-FIFO. The
software can then check these data in comparison with
the scheduled data. If a read instruction is handled, the
interface must set the data word FFH so that the re-
sponding slave can insert its data. In this case the Read-
FIFO contains the read-in data.
2
I C / IM bus Prescaler
2E0H
External addresses, used for EMU boards
to 2E7H
2FEH
2FFH
Reserved, do not use
Reserved for testing purposes
If telegrams longer than 3 bytes are received, (1 ad-
dress, 2 data bytes), the software must check the filling
condition of the control data FIFO and, if necessary, fill
it up (or read out the Read-FIFO). A variety of status
flags is available for this purpose:
2
8.6. I C and IM Bus Interface
– The‘half-full’flagissetiftherearemorethantwobytes
available in the Transmit-FIFO.
The master bus interface can generate two different
kinds of format:
– Bus Busy is activated by writing any byte to any one
of the data transfer registers. It stays active until the
2
2
– I C format
I C or IM bus activities are stopped after the stop
condition generation. So ‘Busy’ becomes inactive af-
ter the data that was written in one of the four registers
to terminate the bus action is completely shifted out,
and the bus-specific stop condition is generated (see
Fig. 2–22, 2–25).
– IM format
The MSBit of the bus prescaler registers (address
2DBH) is used to switch I C_CLK between
2
IM1_CLK_Pad and IM1_ID_Pad. The remaining 7 bits
can be used to set the bit rate.
2
Moreover, in the I C mode the ACK-bit is recorded sepa-
ratelyonthebuslinesfortheaddressandthedatafields;
however, the interface itself can set the address ACK=0.
InanycasethetwoACKflagsshowtheactualbuscondi-
2
bit 7
0 = I C_CLK at IM1_ID_Pad,
2
2
1=I C_CLKatIM1_CLK_Pad(resetstate)
tion. These flags remain until the next I C start condition
bit 6 to 0
bit rate f
= f
/ (4 * n) for n>1
is generated.
IMI2C
OSC
MICRONAS INTERMETALL
67
MICRONAS [ MICRONAS ]
