CAP 3001 A
Pin 39 – QX2/ECLK
Pin 55 – WSI
Crystal pin. This pin has to be connected with the crystal
or with an external clock signal.
DAI-Bus: word select input; this is a control line to sepa-
rate left and right channel in the serial DAI stream.
Pin 40 – RESET
Inthesteadystate, highlevelisrequiredatthispin. Alow
level resets the CAP 3001 A.
Pin 56 – SDIN1
DAI-Bus: serial data input 1.
Pins 57 to 59 – TO1, TO2, TO3
Digital outputs; the logical state can be defined by the
DSP software.
Pins 41 to 43 – IMDATA, IMCLK, IMIDENT
Via these pins the CAP 3001 A sends and receives data
to and from the controller.
Pin 60 – GNDD
This pin serves as ground connection for the digital sig-
nals.
Pin 44 – TEOSC
Test purpose.
Pin 45 – REFCLK
Input for the synthesizer reference frequency.
Pin 61 – VSUPD
Digital supply voltage. Power is supplied via this pin for
the digital circuitry of the CAP 3001 A.
Pins 46 to 48 – TI1, TI2, TI3
Static digital inputs; these signals can be used as a
branch condition in the DSP software. If not used, they
must be connected to GND.
Pin 62 – CLKOUT
This output is used for clocking external hardware.
Pin 49 – SCLKO
DAI-Bus: serial clock output.
Pin 63 – TP3
Test purpose.
Pin 50 – WSO
DAI-Bus: word select output; this is a control line to sep-
arated left and right channel in the serial DAI stream.
Pin 64 – TP2
Test purpose.
Pin 65 – TP4
Test purpose.
Pin 51 – SDOUT
DAI-Bus: serial data output.
Pin 66 – TP1
Test purpose.
Pin 52 – SDIN2
DAI-Bus: serial data input 2.
Pin 67 – AMLEVEL
Input for the AM field strength information.
Pin 53 – ERR
DAI-Bus: error input.
Pin 54 – SCLKI
Pin 68 – MPLEVEL
DAI-Bus: serial clock input.
Input for the multipath information.
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