256Mb and 512Mb (256Mb/256Mb), P30-65nm
Program Operations
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written to
the flash memory array. Subsequent writes provide additional device addresses and da-
ta. All data addresses must lie within the start address plus the word count. Optimum
programming performance and lower power usage are obtained by aligning the starting
address at the beginning of a 512-word boundary (A[9:1] = 0x00 for Easy BGA and TSOP,
A[8:0] for QUAD+ package; see Part Numbering Information). The maximum buffer size
would be 256-word if the misaligned address range is crossing a 512-word boundary
during programming.
After the last data is written to the buffer, the BUFFERED PROGRAMMING CONFIRM
command must be issued to the original block address. The device begins to program
buffer contents to the array. If a command other than the BUFFERED PROGRAMMING
CONFIRM command is written to the device, a command sequence error occurs and
SR[7,5,4] are set. If an error occurs while writing to the array, the device stops program-
ming, and SR[7,4] are set, indicating a programming failure.
When buffered programming has completed, additional buffer writes can be initiated
by issuing another BUFFERED PROGRAMMING SETUP command and repeating the
buffered program sequence. Buffered programming may be performed with VPP = VPPL
or VPPH (see Operating Conditions for limitations when operating the device with VPP
VPPH).
=
If an attempt is made to program past an erase-block boundary using the BUFFERED
PROGRAM command, the device aborts the operation. This generates a command se-
quence error, and SR[5,4] are set.
If buffered programming is attempted while VPP is at or below VPPLK, SR[4,3] are set. If
any errors are detected that have set status register bits, the status register should be
cleared using the CLEAR STATUS REGISTER command.
Buffered Enhanced Factory Programming (80h, D0h)
Buffered enhanced factory programming (BEFP) speeds up multilevel cell (MLC) pro-
gramming. The enhanced programming algorithm used in BEFP eliminates traditional
programming elements that drive up overhead in device programmer systems.
BEFP consists of three phases: setup, program/verify, and exit (see the BEFP Flowchart).
It uses a write buffer to spread MLC program performance across 512 data words. Verifi-
cation occurs in the same phase as programming to accurately program the cell to the
correct bit state.
A single two-cycle command sequence programs the entire block of data. This en-
hancement eliminates three write cycles per buffer: two commands and the word count
for each set of 512 data words. Host programmer bus cycles fill the device write buffer
followed by a status check. SR0 indicates when data from the buffer has been program-
med into sequential array locations.
Following the buffer-to-flash array programming sequence, the device increments in-
ternal addressing to automatically select the next 512-word array boundary. This aspect
of BEFP saves host programming equipment the address bus setup overhead.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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