256Mb and 512Mb (256Mb/256Mb), P30-65nm
Program Operations
Program Operations
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be de-asserted and the block must be unlocked before at-
tempting to program the block. Attempting to program a locked block causes a program
error (SR4 and SR1 set) and termination of the operation. See Security Modes for details
on locking and unlocking blocks.
Word Programming (40h)
Word programming operations are initiated by writing the WORD PROGRAM SETUP
command to the device (see the Command Codes and Definitions table). This is fol-
lowed by a second write to the device with the address and data to be programmed. The
device outputs status register data when read (see the Word Program Flowchart). VPP
must be above VPPLK, and within the specified VPPL MIN/MAX values.
During programming, the device executes a sequence of internally-timed events that
program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the array changes 1s to 0s. Memory array bits
that are 0s can be changed to 1s only by erasing the block (see Erase Operations).
The status register can be examined for programming progress and errors by reading at
any address. The device remains in the read status register state until another com-
mand is written to the device.
SR7 indicates the programming status while the sequence executes. Commands that
can be issued to the device during programming are PROGRAM SUSPEND, READ STA-
TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and READ ARRAY (this returns
unknown data).
When programming has finished, SR4 (when set) indicates a programming failure. If
SR3 is set, the device could not perform the WORD PROGRAMMING operation because
VPP was outside of its acceptable limits. If SR1 is set, the WORD PROGRAMMING opera-
tion attempted to program a locked block, causing the operation to abort.
Before issuing a new command, the status register contents should be examined and
then cleared using the CLEAR STATUS REGISTER command. Any valid command can
follow, when word programming has completed.
Buffered Programming (E8h, D0h)
The device features a 512-word buffer to enable optimum programming performance.
For buffered programming, data is first written to an on-chip write buffer. Then the buf-
fer data is programmed into the array in buffer-size increments. This can improve sys-
tem programming performance significantly over non-buffered programming.
When the BUFFERED PROGRAMMING SETUP command is issued, status register in-
formation is updated and reflects the availability of the buffer. SR7 indicates buffer
availability: if set, the buffer is available; if cleared, the buffer is not available.
Note: The device default state is to output SR data after the BUFFERED PROGRAM-
MING SETUP command. CE# and OE# LOW drive device to update status register. It is
not allowed to issue 70h to read SR data after E8h command; otherwise, 70h would be
counted as word count.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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