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N25Q512A83GSF40G 参数 Datasheet PDF下载

N25Q512A83GSF40G图片预览
型号: N25Q512A83GSF40G
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Signal Descriptions  
Table 1: Signal Descriptions (Continued)  
Symbol  
Type  
Description  
HOLD#  
Control  
Input  
HOLD: Pauses any serial communications with the device without deselecting the device. DQ1  
(output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device  
must be selected with S# driven LOW.  
HOLD# is used for input/output during the following operations: QUAD OUTPUT FAST READ,  
QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED  
FAST PROGRAM.  
In QIO-SPI, HOLD# acts as an I/O (DQ3 functionality), and the HOLD# functionality is disabled  
when the device is selected. When the device is deselected (S# is HIGH) in parts with RESET#  
functionality, it is possible to reset the device unless this functionality is not disabled by means  
of dedicated registers bits.  
The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR.  
On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a  
DTR operation is recognized.  
W#  
Control  
Input  
Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in  
extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the  
voltage range applied to the signal. If voltage range is low (0V to VCC), the signal acts as a  
write protection control input. The memory size protected against PROGRAM or ERASE opera-  
tions is locked as specified in the status register block protect bits 3:0.  
W# is used as an input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD  
INPUT/OUTPUT FAST READ operations and in QIO-SPI.  
VPP  
Power  
Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power  
supply, as defined in the AC Measurement Conditions table.  
During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the addition-  
al VPP power supply to speed up internal operations. However, to enable this functionality, it is  
necessary to set bit 3 of the VECR to 0.  
In this case, VPP is used as an I/O until the end of the operation. After the last input data is shif-  
ted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal  
operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations  
start at standard speed.  
The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is  
disabled.  
VCC  
VSS  
Power  
Device core power supply: Source voltage.  
Ground: Reference for the VCC supply voltage.  
Do not use.  
Ground  
DNU  
NC  
No connect.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2011 Micron Technology, Inc. All rights reserved.