Instructions
N25Q128 - 1.8 V
Table 16. Read Identification data-out sequence
Manufacturer
Device identification
Identification
UID
Memory type
BBh
Memory capacity EDID+CFD length
18h 10h
EDID
CFD
20h
2 bytes
14 bytes
Table 17. Extended Device ID table (first byte)
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Architecture:
00 = Uniform,
01 = Bottom,
11 = Top
VCR XIP bit setting: Hold/Reset function:
Addressing:
0 = by Byte,
Reserved Reserved Reserved 0 = required,
1 = not required
0 = HOLD,
1 = Reset
Figure 10. Read identification instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18
28 29 30 31
C
Instruction
DQ0
Manufacturer identification
Device identification
UID
High Impedance
DQ1
15 14 13
MSB
3
2
1
0
MSB
MSB
AI06809d
9.1.2
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
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