Instructions
N25Q128 - 1.8 V
9.2.26
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Release from Deep-Power-down (RDP)
instruction of the Extended SPI protocol. The instruction sequence is shown in Figure 71:
Release from Deep Power-down instruction sequence.
Figure 71. Release from Deep Power-down instruction sequence
S
t
RDP
0
1
2
3
C
Instruction
DQ0
DQ1
High Impedance
Deep power-down mode Standby mode
Dual_RDP
9.3
QIO-SPI Instructions
In QIO-SPI protocol, instructions, addresses and Input/Output data always run in parallel on
four wires: DQ0, DQ1, DQ2 and DQ3 with the already mentioned exception of the modify
instruction (erase and program) performed with the VPP=VPPh.
In the case of a Quad Command Fast Read (QCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID)
instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Quad Command Page Program (QCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write
Enhanced Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR),
Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven
High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.
132/185
MICRON [ MICRON TECHNOLOGY ]
