64Mb : x4, x8, x16
SDRAM
1
WRITE – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
2
A0-A9, A11
ROW
t
COLUMN m
AS
AH
ENABLE AUTO PRECHARGE
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DIN m
DIN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
TIMING PARAMETERS
-6
-7 E
-7 5
-8 E
-6
-7 E
-7 5
-8 E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
AH
1
1.5
2.5
2.5
6
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
DH
1.5
1
1.5
0.8
1.5
0.8
1.5
15
1.5
0.8
1.5
0.8
1.5
20
2
1
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
CH
3
1.5
1
2
CL
3
1
CK(3)
CK(2)
CKH
8
DS
1.5
18
2
–
7.5
0.8
10
1
RCD
20
1
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
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