64Mb : x4, x8, x16
SDRAM
1
READ – DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
t
CKS CKH
CKE
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM /
DQML, DQMH
t
t
t
AH
AS
2
A0-A9, A11
A10
ROW
COLUMN m
t
AS
AH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
t
t
AC
t
t
t
t
OH
AC
OH
AC
OH
D
OUT
m
DOUT m + 2
D
OUT m + 3
DQ
t
LZ
t
t
t
HZ
LZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-7 E
-7 5
-8 E
-6
-7 E
-7 5
-8 E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
AC(3)
AC(2)
AH
5.5
–
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
HZ(3)
HZ(2)
LZ
1.5
1
1.5
0.8
1.5
1.5
0.8
1.5
2
1
2
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
1.5
2.5
2.5
6
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
1.5
AS
5.5
–
5.4
5.4
5.4
6
6
6
CH
3
CL
3
1
2
1
3
1
3
1
3
CK(3)
CK(2)
CKH
8
OH
–
7.5
0.8
10
1
RCD
18
15
20
20
1
0.8
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
47
MICRON [ MICRON TECHNOLOGY ]
