64Mb : x4, x8, x16
SDRAM
1
SINGLE WRITE – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
4
4
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
3
A0-A9, A11
ROW
t
COLUMN m
AS
AH
AH
ALL BANKS
ROW
t
ROW
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
BA0, BA1
BANK
BANK
t
t
DH
DS
DIN
m
DQ
2
t
t
t
t
t
RCD
RAS
RC
RP
WR
DON’T CARE
TIMING PARAMETERS
-6
-7 E
-7 5
-8 E
-6
-7 E
-7 5
-8 E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
AH
1
1.5
2.5
2.5
6
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
1
1.5
0.8
1.5
1.5
0.8
1.5
2
1
2
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
CH
3
1.5
CL
3
RAS
RC
42 120,000 37 120,000 44 120,000 50 120,000 ns
CK(3)
CK(2)
CKH
CKS
CMH
8
60
18
18
12
60
15
15
14
66
20
20
15
70
20
20
15
ns
ns
ns
ns
–
7.5
0.8
1.5
0.8
10
1
RCD
RP
1
0.8
1.5
0.8
1.5
1
2
WR
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
4. PRECHARGE command not allowed else RASwould be violated.
t
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
50
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