256Mb: x4, x8, x16 SDRAM
Mode Register
Figure 19: Mode Register Definition
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Mode Register (Mx)
Burst Length
11 10
3
1
0
12
8
6
5
2
9
4
7
Op Mode
WB
CAS Latency
BT
Burst Length
Reserved
Program
BA1, BA0 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
Write Burst Mode
M9
0
4
4
Programmed Burst Length
Single Location Access
8
8
1
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
M8
M7
0
M6-M0
Defined
–
Operating Mode
0
–
Standard Operation
–
All other states reserved
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
Reserved
Reserved
2
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
45
© 1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
