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MT48LC64M4A2FB1 参数 Datasheet PDF下载

MT48LC64M4A2FB1图片预览
型号: MT48LC64M4A2FB1
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM [SDR SDRAM]
分类和应用: 动态存储器
文件页数/大小: 86 页 / 3693 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb: x4, x8, x16 SDRAM  
Truth Tables  
Table 17: Truth Table – CKE  
Notes 1–4 apply to all parameters and conditions  
Current State  
Power-down  
Self refresh  
CKEn-1  
CKEn  
Commandn  
Actionn  
Notes  
L
L
X
Maintain power-down  
Maintain self refresh  
Maintain clock suspend  
Exit power-down  
X
Clock suspend  
Power-down  
Self refresh  
X
L
H
L
COMMAND INHIBIT or NOP  
COMMAND INHIBIT or NOP  
X
5
6
7
Exit self refresh  
Clock suspend  
All banks idle  
All banks idle  
Reading or writing  
Exit clock suspend  
Power-down entry  
Self refresh entry  
Clock suspend entry  
H
COMMAND INHIBIT or NOP  
AUTO REFRESH  
VALID  
H
H
See Table 16 (page 39).  
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previ-  
ous clock edge.  
Notes:  
2. Current state is the state of the SDRAM immediately prior to clock edge n.  
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of  
COMMANDn.  
4. All states and sequences not shown are illegal or reserved.  
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time  
for clock edge n + 1 (provided that tCKS is met).  
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after  
tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges  
occurring during the tXSR period. A minimum of two NOP commands must be provided  
during the tXSR period.  
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-  
nize the next command at clock edge n + 1.  
PDF: 09005aef8091e6d1  
256Mb_sdr.pdf - Rev. R 10/12 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
41  
© 1999 Micron Technology, Inc. All rights reserved.  
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