256Mb: x4, x8, x16 SDRAM
Initialization
Note:
More than two AUTO REFRESH commands can be issued in the sequence. After steps 9
and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC
loops is achieved.
Figure 18: Initialize and Load Mode Register
T0
T1
Tn + 1
To + 1
CL
Tp + 1
Tp + 2
Tp + 3
( (
) )
( (
) )
( (
) )
t
t
CK
CK
((
))
t
( (
) )
( (
) )
( (
) )
CH
t
t
CKH
CKS
((
))
((
))
( (
) )
( (
) )
( (
) )
( (
) )
CKE
t
t
CMS CMH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQM/
DQML, DQMU
5
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A[9:0],
CODE
ROW
ROW
BANK
A[12:11]
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
A10
CODE
SINGLE BANK
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
ALL
BANKS
BA0, BA1
DQ
High-Z
((
))
((
))
T = 100µs
MIN
t
t
t
t
MRD
RP
RFC
RFC
Power-up:
Program Mode Register 1, 3, 4
AUTO REFRESH
V
DD and
AUTO REFRESH
Precharge
all banks
CLK stable
DON’T CARE
UNDEFINED
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
Notes:
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at tP + 1.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
43
© 1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
