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MT48LC4M32LFFC 参数 Datasheet PDF下载

MT48LC4M32LFFC图片预览
型号: MT48LC4M32LFFC
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 61 页 / 1390 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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ADVANCE  
128Mb: x16, x32  
MOBILE SDRAM  
TRUTH TABLE 2 – CKE  
(Notes: 1-4)  
CKE  
CKE  
CURRENT STATE  
Power-Down  
COMMAND  
ACTION  
n
NOTES  
n-1  
n
n
L
L
X
X
X
Maintain Power-Down  
Maintain Self Refresh  
Maintain Clock Suspend  
Exit Power-Down  
Self Refresh  
Clock Suspend  
Power-Down  
L
H
L
COMMAND INHIBIT or NOP  
COMMAND INHIBIT or NOP  
X
5
6
7
Self Refresh  
Exit Self Refresh  
Clock Suspend  
All Banks Idle  
All Banks Idle  
Reading or Writing  
Exit Clock Suspend  
Power-Down Entry  
Self Refresh Entry  
H
H
COMMAND INHIBIT or NOP  
AUTO REFRESH  
VALID  
Clock Suspend Entry  
H
See Truth Table 3  
NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.  
2. Current state is the state of the SDRAM immediately prior to clock edge n.  
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.  
4. All states and sequences not shown are illegal or reserved.  
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1  
(provided that tCKS is met).  
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT  
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP  
commands must be provided during tXSR period.  
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at  
clock edge n + 1.  
128Mb: x16, x32 Mobile SDRAM  
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2002, Micron Technology, Inc.  
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