64Mb: x4, x8, x16 SDRAM
WRITE Operation
Figure 31: WRITE-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
t
t
WR @ CK ≥ 15ns
DQM
t
RP
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
Command
Address
Bank
(a or all)
Bank a,
Col n
Bank a,
Row
t
WR
D
D
IN
IN
DQ
t
t
WR @ CK < 15ns
DQM
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
Command
Address
Bank
(a or all)
Bank a,
Col n
Bank a,
Row
t
WR
D
D
IN
IN
DQ
Transitioning data
Don’t Care
1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Note:
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at
that time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 32 (page 60), where data n is the last desired data
element of a longer burst.
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
59
© 1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
