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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
WRITE Operation  
WRITE Operation  
WRITE bursts are initiated with a WRITE command, as shown in Figure 12 (page 31).  
The starting column and bank addresses are provided with the WRITE command and  
auto precharge is either enabled or disabled for that access. If auto precharge is ena-  
bled, the row being accessed is precharged at the completion of the burst. For the ge-  
neric WRITE commands used in the following figures, auto precharge is disabled.  
During WRITE bursts, the first valid data-in element is registered coincident with the  
WRITE command. Subsequent data elements are registered on each successive positive  
clock edge. Upon completion of a fixed-length burst, assuming no other commands  
have been initiated, the DQ will remain at High-Z and any additional input data will be  
ignored (see Figure 27 (page 56)). A continuous page burst continues until terminated;  
at the end of the page, it wraps to column 0 and continues.  
Data for any WRITE burst can be truncated with a subsequent WRITE command, and  
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE  
command. The new WRITE command can be issued on any clock following the previ-  
ous WRITE command, and the data provided coincident with the new command ap-  
plies to the new command (see Figure 28 (page 57)). Data n + 1 is either the last of a  
burst of two or the last desired data element of a longer burst.  
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-  
sociated with a prefetch architecture. A WRITE command can be initiated on any clock  
cycle following a previous WRITE command. Full-speed random write accesses within a  
page can be performed to the same bank, as shown in Figure 29 (page 58), or each  
subsequent WRITE can be performed to a different bank.  
Figure 27: WRITE Burst  
T0  
T1  
T2  
T3  
CLK  
WRITE  
NOP  
NOP  
NOP  
Command  
Address  
DQ  
Bank,  
Col n  
DIN  
DIN  
Transitioning data  
1. BL = 2. DQM is LOW.  
Don’t Care  
Note:  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
56  
© 1999 Micron Technology, Inc. All rights reserved.