128Mb: x4, x8, x16
SDRAM
1
WRITE – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
NOP
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
3
A0-A9, A11
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
MAX
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MIN
1.5
0.8
1.5
44
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
DS
1.5
0.8
1.5
37
60
15
15
14
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AS
1
CH
3
2
CL
3
RAS
RC
120,000
120,000
50
70
20
20
15
120,000
ns
ns
ns
ns
ns
CK (3)
CK (2)
CKH
CKS
CMH
8
66
7.5
0.8
1.5
0.8
10
1
RCD
RP
20
0.8
1.5
0.8
20
2
WR
15
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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