128Mb: x4, x8, x16
SDRAM
1
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9, A11
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 3
t
BANK 3
BANK 0
t
t
t
t
AC
AC
AC
AC
AC
t
t
t
t
t
t
AC
OH
OH
OH
OH
OH
DOUT
m
D
OUT m + 1
D
OUT m + 2
D
OUT m + 3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RCD - BANK 0
CAS Latency - BANK 0
RP - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 3
CAS Latency - BANK 3
RRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
0.8
1.5
1
MAX
MIN
1
MAX UNITS
t
t
AC (3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
LZ
0.8
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
AC (2)
5.4
2
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
1
t
t
t
t
t
t
t
AS
OH
3
3
3
CH
3
RAS
RC
44
60
15
15
14
120,000
44
66
20
20
15
120,000
50
70
20
20
20
120,000
ns
ns
ns
ns
ns
CL
3
CK (3)
CK (2)
CKH
CKS
8
RCD
RP
7.5
0.8
1.5
10
1
0.8
1.5
RRD
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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