128Mb: x4, x8, x16
SDRAM
AUTO REFRESH MODE
T0
T1
T2
Tn + 1
CL
To + 1
( (
) )
( (
) )
t
CLK
CKE
t
t
( (
) )
( (
) )
CK
CH
( (
) )
( (
) )
t
t
t
CKS
CMS
CKH
t
CMH
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
DQM /
DQML, DQMH
( (
) )
( (
) )
A0-A9, A11
A10
ROW
ROW
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BANK(S)
BA0, BA1
DQ
BANK
High-Z
( (
) )
( (
) )
t
t
t
RFC
1
1
RP
RFC
Precharge all
active banks
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
0.8
1.5
0.8
1.5
66
MIN
1
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
CKH
CKS
CMH
CMS
RFC
RP
0.8
1.5
0.8
1.5
66
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
AS
2
2
CH
3
1
CL
3
2
CK (3)
CK (2)
8
70
20
7.5
10
15
20
*CAS latency indicated in parentheses.
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
40
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