128Mb: x4, x8, x16
SDRAM
SELF REFRESH MODE
T0
T1
T2
Tn + 1
To + 1
To + 2
( (
) )
( (
) )
t
CL
CLK
CKE
( (
t
( (
) )
t
CH
CK
) )
t
CKS
RAS min1
t
≥
( (
) )
( (
) )
( (
) )
t
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
or COMMAND
INHIBIT
COMMAND
PRECHARGE
NOP
NOP
( (
) )
( (
) )
( (
) )
( (
) )
DQM/
DQML, DQMH
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11
A10
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
( (
) )
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-7E
-75
MAX
-8E
MAX UNITS
-7E
MAX
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
1
SYMBOL* MIN
MIN
1.5
0.8
1.5
44
MAX
MIN
2
MAX UNITS
t
t
t
t
t
t
t
AH
0.8
1.5
2.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
RAS
RP
1.5
0.8
1.5
37
ns
ns
ns
t
t
t
t
t
t
AS
2
1
CH
3
2
CL
3
120,000
120,000
50
20
80
120,000
ns
ns
ns
CK (3)
CK (2)
CKH
8
15
20
7.5
0.8
10
1
XSR
75
75
0.8
*CAS latency indicated in parentheses.
NOTES:1. No maximum time limit for Self Refresh. tRAS max applies to non-Self Refresh mode.
t
2. XSR requires minimum of two clocks regardless of frequency or timing.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
41