128Mb: x4, x8, x16
SDRAM
NOTES
t
t
1. All voltages referenced to VSS.
15. Timing actually specified by WR plus RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ TA ≤ +70°C and -
40°C ≤ TA ≤ +85°C for IT parts) is ensured.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency alter-
ation for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
6. An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ
must be powered up simultaneously. VSS and VSSQ
mustbeatsamepotential.)ThetwoAUTOREFRESH
command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
21. Based on tCK = 10ns for -8E and tCK = 7.5ns for -75 and
-7E .
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width
≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifica-
tion, theclockandCKEmusttransitbetweenVIH and
VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
t
or precharge states (READ, WRITE, including WR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
Q
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7ns for -7E, 7.5ns for -75, and 7ns
for -8E after the first clock delay, after the last WRITE
is executed. May not exceed limit set for precharge
mode.
50pF
t
10. HZ defines the time at which the output achieves the
25. Precharge mode only.
open circuit condition; it is not a reference to VOH or
VOL. The last valid data element will meet tOH before
going High-Z.
26. JEDEC and PC100 specify three clocks.
27. AC for -75/-7E at CL = 3 with no load is 4.6ns and is
t
guaranteed by design.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with
timing referenced to 1.5V crossover point. If the in-
put transition time is longer than 1 ns, then the
timing is referenced at VIL (MAX) and VIH (MIN) and
no longer at the 1.5V crossover point. Refer to Micron
Technical Note TN-48-09 for more details.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
VIH or VIL levels.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
t
32. For -8E, CL = 2 and CK = 10ns; for -75, CL = 3 and
tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
ally a nominal value and does not result in a fail
value.
13. IDD specifications are tested after the device is prop-
erly initialized.
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
14. Timing actually specified by tCKS; clock(s) specified
as a reference only at minimum cycle rate.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
36
MICRON [ MICRON TECHNOLOGY ]
