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MT48LC8M16A2FB-8EL 参数 Datasheet PDF下载

MT48LC8M16A2FB-8EL图片预览
型号: MT48LC8M16A2FB-8EL
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 59 页 / 1835 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x4, x8, x16  
SDRAM  
CAPACITANCE  
(Note: 2; notes appear on page 36)  
PARAMETER - TSOP “TG” Package  
Input Capacitance: CLK  
SYMBOL  
CI1  
MIN  
2.5  
MAX UNITS NOTES  
3.5  
3.8  
6.0  
pF  
pF  
pF  
29  
30  
31  
Input Capacitance: All other input-only pins  
Input/Output Capacitance: DQs  
CI2  
2.5  
CIO  
4.0  
PARAMETER - FBGA “FB” Package  
Input Capacitance: CLK  
SYMBOL  
CI1  
MIN  
1.5  
MAX UNITS NOTES  
3.5  
3.8  
6.0  
pF  
pF  
pF  
34  
35  
36  
Input Capacitance: All other input-only pins  
Input/Output Capacitance: DQs  
CI2  
1.5  
CIO  
3.0  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED  
AC OPERATING CONDITIONS  
(Notes: 5, 6, 8, 9, 11; notes appear on page 36)  
AC CHARACTERISTICS  
PARAMETER  
Access time from CLK (pos. edge)  
-7E  
-75  
MAX  
-8E  
MIN  
SYMBOL MIN  
MAX  
5.4  
MIN  
MAX  
6
6
UNITS NOTES  
t
CL = 3  
CL = 2  
AC(3)  
5.4  
6
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
27  
t
AC(2)  
5.4  
t
Address hold time  
Address setup time  
CLK high-level width  
CLK low-level width  
Clock cycle time  
AH  
0.8  
1.5  
2.5  
2.5  
7
0.8  
1.5  
2.5  
2.5  
7.5  
10  
1
2
t
AS  
CH  
t
3
t
CL  
3
t
t
CL = 3  
CL = 2  
CK(3)  
CK(2)  
8
23  
23  
7.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
10  
1
t
CKE hold time  
CKH  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
t
CKE setup time  
CKS  
2
t
CS#, RAS#, CAS#, WE#, DQM hold time  
CS#, RAS#, CAS#, WE#, DQM setup time  
Data-in hold time  
CMH  
1
t
CMS  
2
t
DH  
1
t
Data-in setup time  
DS  
2
t
t
Data-out high-impedance time  
CL = 3  
CL = 2  
HZ(3)  
HZ(2)  
5.4  
5.4  
5.4  
6
6
6
10  
10  
t
Data-out low-impedance time  
Data-out hold time (load)  
LZ  
1
3
1
3
1
3
t
OH  
t
Data-out hold time (no load)  
ACTIVE to PRECHARGE command  
ACTIVE to ACTIVE command period  
ACTIVE to READ or WRITE delay  
Refresh period (4,096 rows)  
AUTO REFRESH period  
OH  
1.8  
37  
60  
15  
1.8  
44  
66  
20  
1.8  
50  
70  
20  
28  
N
t
RAS  
120,000  
64  
120,000  
64  
120,000  
64  
t
RC  
t
RCD  
t
REF  
t
RFC  
66  
15  
14  
0.3  
66  
20  
15  
0.3  
70  
20  
20  
0.3  
t
PRECHARGE command period  
ACTIVE bank a to ACTIVE bank b command  
Transition time  
RP  
t
RRD  
t
T
1.2  
1.2  
1.2  
7
t
WRITE recovery time  
WR 1 CLK +  
7ns  
1 CLK +  
7.5ns  
1 CLK +  
7ns  
24  
14  
15  
75  
15  
80  
ns  
ns  
25  
20  
t
Exit SELF REFRESH to ACTIVE command  
XSR  
67  
128Mb: x4, x8, x16 SDRAM  
128MSDRAM_E.p65 Rev. E; Pub. 1/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2001, Micron Technology, Inc.  
34  
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