1Gb: x4, x8, x16 DDR3 SDRAM
Data Setup, Hold, and Derating
Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition
Slew
Rate
tVAC at 175mV (ps)
tVAC at 150mV (ps)
tVAC at 135mV (ps)
(V/ns)
DDR3-800/1066
DDR3-800/1066/1333/1600 DDR3-800/1066/1333/1600 DDR3-1866 DDR3-2133
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
75
57
105
105
113
113
93
73
93
73
50
80
90
70
50
38
30
45
25
5
34
13
30
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
29
Note 1
Note 1
Note 1
Note 1
Note 1
11
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input
signal shall become equal to or less than VIL(ac) level.
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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111
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