1Gb: x4, x8, x16 DDR3 SDRAM
Data Setup, Hold, and Derating
Data Setup, Hold, and Derating
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values (see Table 64 (page 1±0); values come from Ta-
ble 56 (page 09)) to the ΔtDS and ΔtDH derating values (see Table 65 (page 1±8)), re-
spectively. Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the
input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 69
(page 111)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH(AC)/VIL(AC)) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach
VIH/VIL(AC). For slew rates that fall between the values listed in Table 66 (page 1±8), the
derating values may obtained by linear interpolation.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC)
and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for
derating value (see Figure 38 (page 112)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a
tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 4± (page 114)).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min
and the first crossing of VREF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value (see Figure 39 (page 113)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a
tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating val-
ue (see Figure 41 (page 115)).
Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
Symbol
800
75
1066
25
1333
–
1600
–
1866
2133
Unit
ps
Reference
VIH(AC)/VIL(AC)
VIH(AC)/VIL(AC)
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
tDS (base) AC175
tDS (base) AC150
tDS (base) AC135
tDH (base) DC100
Slew Rate Referenced
–
–
–
–
125
165
150
1
75
30
60
65
1
10
40
45
1
ps
115
100
1
68
70
2
53
55
2
ps
ps
V/ns
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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